The present invention relates generally to the field of reconfiguring reprogrammable logic devices, and more particularly to avoiding signal contention within a partially reprogrammable logic device, such as a field programmable gate array (FPGA).
Signal contention can be defined as the simultaneous driving of two or more different signals across a single electrical conductor. Signal contention can cause a full spectrum of problems, from short-term output errors to full-scale device malfunctions. For example, in reprogrammable logic device 100 illustrated in FIG. 1, simultaneously driving a single xe2x80x9cnetxe2x80x9d 104 in interconnect network 102 with both a 1 and a 0 at any one of the illustrated configurable logic blocks (xe2x80x9cCLBsxe2x80x9d CLB1, CLB2, and CLB3) or interconnect points 103 can cause a large current drain. This current drain can heat up the device and possibly burn it out.
One available technique for eliminating the risk of interconnect signal contention in reprogrammable logic devices (such as the XC4000 device illustrated in part in FIG. 1, available from Xilinx, Inc., assignee of the present invention) comprises performing a pre-implementation analysis of a software file representing a configuration to be programmed into the device. If the analysis reveals an unacceptable likelihood of signal contention within the intended device, the data file is rejected and cannot be loaded into the device.
While this technique is effective for older devices wherein all the memory cells must be re-written in order to change any portion of the configuration of the device, a new generation of partially reprogrammable devices renders this and all other known techniques deficient. Unlike a device that can only be completely reconfigured at any time, reconfiguration of a partially reprogrammable device is often limited to one or more memory cells and interconnect nets on the device. And to further complicate the issue, such partial reconfiguration may occur while operation of the remainder of the device is either temporarily suspended or continuing without interruption (rendering impossible the accurate estimation of net driver status at any point in time).
Thus, partial reprogrammability brings about two situations wherein signal contention is a concern, and for which existing contention-avoidance techniques are insufficient. The risk of signal contention is intolerable if a) any portion of the device is to be reconfigured without a thorough and fully accurate analysis in software form, or b) the unaltered area of the device remains active during the partial reconfiguration, and interacts with the newly configured area in an unanticipated way, even if only during temporary changes of state.
There are some partially reconfigurable devices that obviate signal contention issues by providing only a single driver for any single net. For example, the XC6200 FPGA available from Xilinx, Inc. is such a device. However, such a hardware-based solution significantly limits the flexibility and functionality gained from allowing multiple drivers to potentially (but not simultaneously) drive a single net. A new generation of devices available from Xilinx (known as the VIRTEX(trademark) line of FPGAs) allows reprogrammability without limiting the number of drivers that may drive a single net at different times. Thus, for partially reprogrammable devices such as those included in the VIRTEX line and others, there remains a need for a system and method of avoiding signal contention while enabling partial device reconfiguration with a plurality of potential drive sources on a single net.
To address the shortcomings of the available art, the present invention provides a novel method and system for safely reconfiguring a partially or fully reprogrammable logic device by either identifying and temporarily isolating those drivers that present a risk of contention, or temporarily isolating the region of the device to be reconfigured from outside drivers. To eliminate the risk of signal contention during reprogramming, the invention comprises the steps of (and structure and means for) identifying the nets to be reprogrammed, identifying the device drivers that may induce signal contention during or after a new configuration on the identified nets, electrically isolating the identified drivers, and implementing the new configuration. In the alternative, the method provides the steps of identifying a region of the device to be reprogrammed, electrically isolating the identified region from drivers outside the region along the border of the identified region, reconfiguring the region, and reintegrating the region into the function of the total device.